Methods for forming and programming aligned fuses disposed in an integrated circuit

ABSTRACT

An integrated circuit includes a first conductive layer, an insulator layer disposed on the first conductive layer, and a second conductive layer disposed on the insulator layer. A first fuse is disposed in the first conductive layer and provides a first signal, and a second fuse is disposed in the second conductive layer in alignment with the first fuse and provides a second signal.

TECHNICAL FIELD

1. The invention relates generally to integrated circuits (ICs), andmore particularly to an IC that includes a fuse bank having alignedfuses, such as laser fuses, and methods for forming and programming thefuses. By including aligned fuses, the fuse bank occupies significantlyless area of the IC than if it included fuses laid out side by side.

BACKGROUND OF THE INVENTION

2. Makers of today's electronic equipment consistently pressure ICmanufacturers to: (1) reduce the sizes of ICs, and (2) maintain orincrease the number and complexity of the functions the ICs perform.Therefore, IC designers continue to explore and develop new techniquesfor reducing the areas of IC dies without reducing the ICs'capabilities.

3.FIG. 1 is a block diagram of an IC 10, which includes an array 12 ofmemory cells and redundancy circuitry for replacing defective ones ofthe cells. The array 12 includes a matrix array 14 of matrix memorycells that store data and that are arranged in rows and columns. Anaddress generator 18 receives an external address on the ADDRESS bus andgenerates therefrom an internal row address on a bus 20. This internaladdress identifies a respective row of matrix cells in the array 14. Amatrix circuit 21 includes matrix row decoders 22 ₀-22 _(n)—one for eachrow in the matrix array 14—for firing the respective matrix rows.

4. In operation of the IC 10, the 22 ₀-22 _(n) receive a conventionaladdress PRECHARGE signal before the generator 18 generates the rowaddress. Next, the row 22 ₀-22 _(n) receive and decode the row addresson the bus 20. Then, the row decoder 22 corresponding to the addressedrow fires the word line WL of the addressed row. For example, if theaddress generator 18 addresses row 0 in the matrix array 14, then therow 0 decoder 22 ₀ fires the word line WL0 via a firing terminal 25 ₀.

5. Unfortunately, one or more matrix cells in a row of the matrix array14 may be defective and thus unable to reliably store data. For example,the respective word line WL or a part of the defective matrix cell orcells may be short-circuited to other nodes in the IC 10.

6. To prevent a defective matrix cell from rendering the entire IC 10unusable, the array 12 includes an array 23 of redundant memory cells,and the IC 10 includes a redundant circuit 24 for mapping a redundantcell to the address of a defective matrix cell. In one embodiment, theredundant cells are arranged in rows and columns, and the circuit 24maps a redundant row to the address of a matrix row containing one ormore defective matrix cells. The circuit 24 includes a programmableportion 26 and redundant row decoders 28 ₀-28 _(x)—one decoder for eachrow in the redundant array 23—for firing the respective redundant rows.The programmable portion 26 includes a programmable redundancy addresscircuit 30 and a programmable redundancy control circuit 32. Often, thecircuits 30 and 32 contain laser-programmable fuses that are laid outside by side in a lower layer of the IC 10.

7. If one finds a defective row in the matrix array 14, then he programsthe circuit 24 to map a redundant row in the array 23 to the address ofthe defective matrix row. For example, suppose that matrix row 1 isdefective and one wishes to replace it with the redundant row 0. To dothis, he programs the redundancy address circuit 30 to address theredundant row 0—and thus to activate the redundant row decoder 28 ₀—whenever the address generator 18 generates the address of the matrixrow 1. He also programs the redundancy control circuit 32 to enable theredundant row decoder 28 ₀. Therefore, in response to theredundant-row-0 address from the circuit 30 and an enabling controlsignal from the circuit 32, the redundant row decoder 28 ₀ fires theredundant word line RWL0 via a firing terminal 29 ₀.

8. A problem with the matrix circuit 21, however, is that it continuesto fire the word line WL of a defective matrix row even after one hasprogrammed the redundant circuit 24 to replace the defective row with aredundant row. This firing may cause a malfunction that is not fixed bythe mapping of the redundant row to the address of the defective row.For example, if the word line WL of the defective row is shorted toanother word line or to a cell plate, then firing WL may cause dataerrors or other malfunctions.

9.FIG. 2 is a block diagram of an IC 40, which is similar to the IC 10of FIG. 1 except that the matrix circuit 21 does not fire a defectivematrix row. The matrix circuit 21 includes a programmable matrix controlcircuit 42. If one finds a defective matrix row in the array 14, then inaddition to programming the redundant circuit 24 as discussed above inconjunction with FIG. 1, he programs the circuit 42 to disable thecorresponding row decoder 22 from firing the word line WL of thedefective row. For example, if the matrix row 0 is defective, then oneprograms the control circuit 42 to disable the row decoder 22 ₀. Thus,even if the address generator 18 generates the address of the matrix row0, the disabled row decoder 22 ₀ does not fire the word line WL0.

10. Often, the matrix control circuit 42 includes laser fuses that aredisposed in the same layer of the IC 40 as the fuses of the redundantcircuit 24. Therefore, the circuit 42 tends to increase the die area,and thus the overall size, of the IC 40.

11.FIG. 3 is a cutaway cross-sectional view of a semiconductor structure50, which includes a stacked fuse 51. The structure 50 includes an upperfuse element 52 disposed on an insulator layer 54, and includes a lowerfuse element 56 disposed beneath the insulator layer 54 and in alignmentwith the upper fuse element 52. The fuse elements 52 and 56 areelectrically connected in parallel by conductive vias 58 and 59 to formthe stacked fuse 51. Compared to a single fuse element, the stacked fuse51 has approximately the same width, and thus occupies approximately thesame die area, but has approximately twice the current-carryingcapacity. During programming of the stacked fuse 51, one uses a laserbeam to cut both fuse elements 52 and 56.

12. Unfortunately, including stacked fuses in the IC 40 would not reducethe number of fuses in the circuits 30, 32, and 42, and thus would notreduce the die area of the IC 40. In fact, including stacked fuses inthe IC 40 would increase the manufacturing complexity of and could add aconductive layer to the IC 40.

SUMMARY OF THE INVENTION

13. In one aspect of the invention, an IC includes a first conductivelayer, an insulator layer disposed on the first conductive layer, and asecond conductive layer disposed on the insulator layer. A first fuse isdisposed in the first conductive layer and provides a first signal, anda second fuse is disposed in the second conductive layer in alignmentwith the first fuse and provides a second signal.

14. Such an IC includes fuses that are disposed one on top of the other.A fuse bank including such fuses occupies significantly less die areathan a fuse bank including only side-by-side fuses. Therefore, an IChaving such a fuse bank can be significantly smaller than an otherwiseequivalent IC having a side-by-side fuse bank.

BRIEF DESCRIPTION OF THE DRAWINGS

15.FIG. 1 is a block diagram of a conventional IC that fires a defectivematrix cell even after the defective cell is replaced with a redundantcell.

16.FIG. 2 is a block diagram of a conventional IC that does not fire adefective matrix cell after the defective cell is replaced with aredundant cell.

17.FIG. 3 is a cutaway cross-sectional view of a conventional stackedfuse.

18.FIG. 4A is a schematic diagram of a fuse bank according to anembodiment of the invention.

19.FIG. 4B is a cutaway cross-sectional view of an embodiment of thefuse bank of FIG. 4A.

20.FIG. 5 is a schematic diagram of the matrix control circuit of FIG. 2according to an embodiment of the invention.

21.FIG. 6 is a schematic diagram of the redundancy control circuit ofFIG. 2 according to an embodiment of the invention.

22.FIG. 7 is a schematic diagram of a matrix row decoder of FIG. 2according to an embodiment of the invention.

23.FIG. 8 is a schematic diagram of a redundant row decoder of FIG. 2according to an embodiment of the invention.

24.FIG. 9 is a block diagram of an embodiment of a memory circuit thatincludes the fuse bank of FIGS. 4A and 4B.

25.FIG. 10 is a block diagram of an electronic system that includes thememory circuit of FIG. 9.

DETAILED DESCRIPTION OF THE INVENTION

26.FIG. 4A is a schematic diagram of a fuse bank 60 according to anembodiment of the invention. The fuse bank 60 includes an upper sub-bank62 of fuses 64 ₀-64 _(y), which are disposed side by side in a firstconductive layer. The fuse bank 60 also includes a lower sub-bank 66 offuses 68 ₀-68 _(y), which are disposed side by side in a secondconductive layer that is beneath the first conductive layer. Theterminals of the fuses 64 and 68 are respectively coupled to nodes thatare omitted from FIG. 4A for clarity. The fuses 64 in the upper sub-bank62 are preferably vertically aligned with the fuses 68 in the lowersub-bank 66 such that the area of the fuse bank 60 is reduced byapproximately half as compared to a fuse bank having all of the fuses 64and 68 disposed in the same layer. For example, the fuse 64 ₀ isdisposed above and in alignment with the fuse 68 ₀. In one embodiment,the fuses 64 ₀ and 68 ₀ are aligned along a line that is normal to thesurface of the layer in which the fuse 64 ₀ is formed. In anotherembodiment, these fuses are aligned such that one can direct a laserbeam at the fuse 64 ₀, cut through the fuse 64 ₀, and then cut throughthe fuse 68 ₀ without redirecting the beam. Because it is difficult insuch an embodiment to cut the fuse 64 ₀ without cutting the fuse 68 ₀,the circuitry connected to the fuses 64 ₀ and 68 ₀ is designed such thatthe fuses 64 ₀ and 68 ₀ can always have the same state (either opened orclosed). But the fuses 64 ₀ and 68 ₀ can have other relative alignmentsso long as one can cut the lower fuse 68 ₀ with a laser beam after hecuts the upper fuse 64 ₀.

27.FIG. 4B is a cutaway cross-sectional view of the fuse bank 60 takenalong lines A-A of FIG. 4A. As discussed above, the fuse 64 ₀ isdisposed above and in alignment with the fuse 68 ₀. Unlike the stackedfuse 51 of FIG. 3, the fuses 64 ₀ and 68 ₀ are not electricallyconnected in parallel, but instead are connected to provide differentsignals or to provide the same signal to different nodes. For example,in one embodiment, the terminals of the fuse 64 ₀ are connected torespective nodes that are different than the nodes to which theterminals of the fuse 68 ₀ are connected. In another embodiment, oneterminal of each of the fuses 64 ₀ and 68 ₀ is connected to a commonnode, and the other terminals are connected to different nodes.

28. The fuses 64 and 68 of the fuse bank 60 can be formed from anysuitable conductive material such as aluminum or polysilicon.Furthermore, the fuse bank 60 may have more than two sub-banks disposedone atop the other.

29. In a related embodiment, the fuses 64 in the upper sub-bank 62 aredesigned to open if exposed to a laser beam that is tuned to a firstfrequency, and the fuses 68 in the lower sub-bank 66 are designed toopen if exposed to a laser beam that is tuned to a second frequency.Therefore, one can cut the fuse 64 ₀ without cutting or damaging thefuse 68 ₀. If it is desired to open both of the fuses 64 ₀ and 68 ₀,then after cutting the fuse 64 ₀ with a laser beam having the firstfrequency, one cuts the fuse 68 ₀ with a laser beam having the secondfrequency. This allows one to design the circuitry connected to thefuses 64 ₀ and 68 ₀ for three possible fuse states: both closed, 64 ₀opened and 68 ₀ closed, and both opened. Conductive materials suitableand lasers for this embodiment of the fuses 64 and 68 are known in theart.

30.FIG. 5 is a schematic diagram of an embodiment of the programmablematrix circuit 42 of FIG. 2 according to the invention. The circuit 42includes the sub-bank 62 of the fuse bank 60 of FIGS. 4A and 4B. In thisembodiment, the sub-bank 62 includes three fuses 64 ₀-64 ₂, although inother embodiments the sub-bank 62 may include more or fewer fuses. Eachof the fuses 64 is serially connected to a respective complimentary pairof an NMOS transistor 70 and a PMOS transistor 72. The gates of the NMOStransistors 70 are all coupled to receive an EVALUATE signal, and thegates of the PMOS transistors 72 are coupled to receive the PRECHARGEsignal. The drains of each pair of transistors 70 and 72 are coupled toa respective line of a bus 74, which connects the transistors 70 and 72to a matrix match circuit 76. The circuit 76 generates control signalson a matrix control bus 77 to enable/disable the respective matrix rowdecoders 22 of FIG. 2.

31. During operation of the matrix circuit 42, all of the transistors 70and 72 function as switches and are initially off. Next, PRECHARGEtransitions from logic 1 to logic 0 to turn on the transistors 72.Because the transistors 70 are turned off, the active transistors 72charge the respective lines of the bus 74 to Vcc, i.e., logic 1. Then,PRECHARGE transitions back to logic 1 to turn off the transistors 72.Next, EVALUATE transitions from logic 0 to logic 1 to turn on all of thetransistors 70. If a fuse 64 is closed, then the respective transistor70 pulls down the respective line of the bus 74 to logic 0. For example,if the fuse 64 ₀ is closed, then the active transistor 70 ₀ dischargesthe respective line of the bus 74 to ground via the fuse 64 ₀, thustransitioning the bus line from logic 1 to logic 0. Conversely, if afuse 64 is opened, then the respective transistor 70 cannot pull downthe respective bus line, which thus retains its precharged level oflogic 1. For example, if the fuse 64 ₀ is opened, then the source of theactive transistor 70 ₀ floats electrically such that the transistor 70 ₀cannot discharge the respective bus line to ground. If all of the fuses64 ₀-64 ₂ are closed, then all of the lines of the bus 74 are at logic 0and the matrix match circuit 76 enables all of the row decoders 22 (FIG.2). Conversely, if one or more of the fuses 64 ₀-64 ₂ are opened, thensome or all of the lines of the bus 74 retain their precharged level oflogic 1. The matrix match circuit 76 decodes the pattern of logic 1s andlogic 0s on the lines of the bus 74, and using conventional logic,disables the appropriate row decoder or decoders 22.

32. In an embodiment of the circuit 42 that can disable at most onematrix row at a time, the three fuses 64 ₀-64 ₂ allow the circuit 42 tohandle up to seven matrix rows, and thus up to seven matrix row decoders22 (FIG. 2). For example, if the circuit 42 handles seven matrix rows,then there are seven unique disable possibilities in that the circuit 42can disable any one of the matrix rows. There is also an additionalpossibility that the circuit 42 disables none of the matrix rows. Thisis a total of eight possibilities, which is the maximum number (2³) thatthe three fuses 64 ₀-64 ₂ can provide for. Of course, one may wish todesign the circuit 42 to handle more than seven matrix rows or todisable more than one matrix row at a time. To do this, he can increasethe number of fuses 64, transistors 70 and 72, and lines of the bus 74,and can redesign the circuit 76 to accommodate the additional bus-lineinputs according to conventional circuit-design principles.

33.FIG. 6 is a schematic diagram of an embodiment of the redundancycontrol circuit 32 of FIG. 2 that is similar to the matrix controlcircuit 42 of FIG. 5. The circuit 32 includes the lower sub-bank 66 ofthe fuse bank 60 of FIG. 4A. In this embodiment, the sub-bank 66includes three fuses 68 ₀-68 ₂, although more or fewer fuses can beincluded. The circuit 32 also includes complementary pairs of NMOS andPMOS transistors 80 and 82, which precharge and evaluate the respectivelines of a bus 84 in response to PRECHARGE and EVALUATE, respectively,according to the respective states of the fuses 68 ₀-68 ₂. The circuit32 also includes a redundant match circuit 86, which generates controlsignals on a redundant control bus 87 to enable/disable the respectiveredundant row decoders 28 of FIG. 2.

34. During operation of the circuit 32, the transistors 80 and 82operate in a manner similar to the transistors 70 and 72 of FIG. 5. Ifall of the fuses 68 are closed, then the redundant match circuit 86disables all of the redundant row decoders 28, and thus all of theredundant rows. If one or more of the fuses are opened, then the circuit86 decodes the pattern of logic 1s and logic 0s on the lines of the bus84, and using conventional logic, enables the appropriate row decoder ordecoders 28. If the circuit 86 is designed to enable one redundant rowdecoder 28 at a time, the three fuses 68 ₀-68 ₂ allow the circuit 86 tohandle up to seven redundant row decoders 28, and thus up to sevenredundant rows. But the circuit 32 can be modified according toconventional circuit-design principles to handle more redundant rowdecoders or to enable more than one decoder 28 at a time.

35. Referring to FIGS. 2, 5, and 6, an embodiment of the IC 40 isdiscussed that illustrates the advantages provided by the fuse bank 60of FIGS. 4A and 4B. In this embodiment, the IC 40 includes seven rowdecoders 22 ₀-22 ₆ and the matrix control circuit 42 of FIG. 5.Furthermore, the IC 40 includes one redundant row decoder 28 ₀ and aslightly modified version of the redundancy control circuit 32 of FIG.6. In the modified circuit 32, the redundant match circuit 86 isdesigned to enable the redundant row decoder 28 ₀ if at least one of thefuses 68 ₀-68 ₂ is opened.

36. For example purposes, suppose that one of the matrix rows in thematrix array 14 is defective, and that one must open the fuse 64 ₀ (FIG.5) so that the matrix match circuit 76 disables the defective row. Bycutting the fuse 64 ₀ with a laser beam and then cutting the fuse 68₀—which is beneath and aligned with the fuse 64 ₀—with the same laserbeam, one disables the respective matrix row decoder 22 from firing thedefective matrix row and enables the redundant row decoder 28 ₀ to firethe corresponding redundant row in its place. Thus, including onesub-bank 62 of the fuse bank 60 in the circuit 42 and the other sub-bank66 in the circuit 32 allows one to program both the redundant and matrixcontrol circuits 32 and 42 by cutting both fuses 64 and 68 in one ormore aligned fuse pairs. Furthermore, this allows the IC 40 to have boththe ability to disable a defective matrix row and the smaller layoutarea of the IC 10 of FIG. 1. In another embodiment that gives similaradvantages, the fuses 64 are designed to open if exposed to a laser beamtuned to a first frequency and the fuses 68 are designed to open ifexposed to a laser beam tuned to a second frequency. This embodimentprovides more design flexibility for the circuits 32 and 42 because afuse 64 of a fuse pair can be opened and the fuse 68 of the pair canremain closed as discussed above in conjunction with FIGS. 4A and 4B.

37. Still referring to FIGS. 5 and 6, although the circuit 42 isdescribed as incorporating the upper sub-bank 62 of the fuse bank 60 andthe circuit 32 is described as incorporating the lower sub-bank 66, thecircuit 42 may incorporate the lower sub-bank 66 and the circuit 32 mayincorporate the upper sub-bank 62. Furthermore, although the matrixcircuit 21 and the redundancy circuit 24 are described as accessing rowsof matrix and redundant cells, respectively, the circuits 21 and 24 canbe designed to access columns or other groupings of matrix and redundantcells. Or, the circuits 21 and 24 can be designed to access individualmatrix and redundant cells. Additionally, although described as beingincluded in the circuits 21 and 24, the fuse bank 60 may be used inother types circuits.

38.FIG. 7 is a schematic diagram of an embodiment of a matrix rowdecoder 22 of FIG. 2 according to the invention. In this embodiment, thematrix circuit 21 can handle up to four matrix rows, and thus four rowdecoders 22. But one can modify the decoder 22 according to conventionalcircuit design principles so that the circuit 21 can accommodate morethan four matrix rows. The decoder 22 includes a PMOS transistor 90having a gate coupled to receive PRECHARGE, an inverter 92 for firingthe word line WL, and three serially connected NMOS transistors 94, 96and 98. The transistors 94 and 96 receive matrix address bits MA1 andMA2, respectively, from the address bus 20 (FIGS. 2), and the transistor98 receives a respective MATRIX CONTROL signal from the matrix matchcircuit 76 (FIG. 5).

39. During testing of the IC 40 (FIG. 2), if the matrix rowcorresponding to the row decoder 22 is functional, then one enables thedecoder 22 by programming the matrix control circuit 42 to generateMATRIX CONTROL equal to logic 1. Conversely, if the matrix row isdefective, then one disables the decoder 22 by programming the circuit42 to generate MATRIX CONTROL equal to logic 0.

40. In operation, before the row address generator 18 (FIG. 2) generatesthe row address on the bus 20, PRECHARGE transitions from logic 1 tologic 0 to turn on the transistor 90. The NMOS transistors 94 and 96(and possibly the transistor 98) are off so that the transistor 90charges the input terminal of the inverter 92 to logic 1. PRECHARGE thentransitions back to logic 1 to turn off the transistor 90, and theaddress generator 18 generates an address. If MATRIX CONTROL equalslogic 0, then the decoder 22 cannot fire the word line WL regardless ofthe values of the address bits MA1 and MA1. Specifically, the logic 0turns off the transistor 98, which acts as an open circuit between theinput terminal of the inverter 92 and ground. This open circuit causesthe input of the inverter 92 to remain at logic 1, which causes theinverter 92 to generate inactive logic 0 on the row line WL. If MATRIXCONTROL equals logic 1, but none or only one of the address bits MA1 andMA2 equal to logic 1, then at least one of the transistors 94 and 96 isturned off. Therefore, there is still an open circuit between the inputterminal of the inverter 92 and ground, and the inverter 92 stillgenerates inactive logic 0 on WL. Conversely, if MATRIX CONTROL, MA1,and MA2 equal logic 1, then all three transistors 94, 96, and 98 are onand together pull the input of the inverter 92 to ground. This causesthe inverter 92 to fire the row by generating active logic 1 on the wordline WL.

41.FIG. 8 is a schematic diagram of an embodiment of a redundant rowdecoder 28 of FIG. 2 according to the invention. The decoder 28 issimilar in structure and operation to the matrix row decoder 22 of FIG.7. In this embodiment, the redundant circuit 24 can handle up to fourredundant rows, and thus four redundant row decoders 28. But one canmodify the decoder 22 according to conventional circuit designprinciples so that the circuit 24 can accommodate more than fourredundant rows. The decoder 28 includes a PMOS transistor 100 having agate coupled to receive PRECHARGE, an inverter 102 for firing theredundant word line RWL, and three serially connected NMOS transistors104, 106, and 108. The transistors 104 and 106 receive redundant addressbits RA1 and RA2, respectively, from the redundant address bus 30 (FIGS.2), and the transistor 108 receives a respective REDUNDANT CONTROLsignal from the redundant match circuit 86 (FIG. 6).

42. During testing of the IC 40 (FIG. 2), if one wishes to replace adefective matrix row with the redundant row corresponding to the decoder28, then he enables the decoder 28 by programming the redundant controlcircuit 32 to generate REDUNDANT CONTROL equal to logic 1. He alsoprograms the redundancy address circuit 30 to generate RA1 and RA2 equalto logic 1 whenever the address generator 18 generates the address ofthe defective matrix row. Conversely, if one does not wish to use theredundant row to replace a defective matrix row, he disables the decoder28 by programming the circuit 32 to generate REDUNDANT CONTROL equal tologic 0.

43. In operation, before the row address generator 18 (FIG. 2) generatesthe row address on the bus 20, PRECHARGE transitions from logic 1 tologic 0 to turn on the transistor 100. The NMOS transistors 104 and 106(and possibly the transistor 108) are off so that the transistor 100charges the input terminal of the inverter 102 to logic 1. PRECHARGEthen transitions back to logic 1 to turn off the transistor 100 and theaddress generator 18 generates a matrix-row address on the bus 20. IfREDUNDANT CONTROL equals logic 0, then the decoder 28 cannot fire theredundant word line RWL regardless of the values of the redundantaddress bits RA1 and RA1. Specifically, the logic 0 turns off thetransistor 108, which acts as an open circuit between the input terminalof the inverter 102 and ground. This open circuit causes the input ofthe inverter 102 to remain at logic 1, which causes the inverter 102 togenerate inactive logic 0 on the row line RWL. If REDUNDANT CONTROLequals logic 1, but none or only one of the bits RA1 and RA2 equal logic1, then at least one of the transistors 104 and 106 is turned off.Therefore, there is still an open circuit between the input terminal ofthe inverter 102 and ground, and the inverter 102 still generatesinactive logic 0 on RWL. Conversely, if REDUNDANT CONTROL, RA1, and RA2equal logic 1, then all three transistors 104, 106, and 108 are on andtogether pull the input of the inverter 102 to ground. This causes theinverter 102 to fire the row by generating active logic 1 on RWL.

44.FIG. 9 is a block diagram of a memory circuit 130, which includes thefuse bank 60 of FIGS. 4A and 4B or the matrix and redundant controlcircuits 42 and 32 of FIGS. 5 and 6, respectively.

45. The memory circuit 130 includes an address register 132, whichreceives an address from an ADDRESS bus. A control logic circuit 134receives a clock (CLK) signal, and receives clock enable (CKE), chipselect ({overscore (CS)}), row address strobe ({overscore (RAS)}),column address strobe ({overscore (CAS)}), and write enable ({overscore(WE)}) signals from the COMMAND bus, and communicates with the othercircuits of the memory device 130. A row address multiplexer 136receives the address signal from the address register 132 and providesthe row address to the row-address latch-and-decode circuits 138 a and138 b for the memory bank 140 a or 140 b, respectively. In oneembodiment, the multiplexer 136 includes the address generator 18 (FIG.2), and the circuits 138 a and 138 b each include the matrix andredundant control circuits 42 and 32 (FIGS. 5 and 6, respectively).

46. During read and write cycles, the row-address latch-and-decodecircuits 138 a and 138 b activate the word lines of the addressed rowsof memory cells in the memory banks 140 a and 140 b, respectively.Read/write circuits 142 a and 142 b read data from the addressed memorycells in the memory banks 140 a and 140 b, respectively, during a readcycle, and write data to the addressed memory cells during a writecycle. A column-address latch-and-decode circuit 144 receives theaddress from the address register 132 and provides the column address ofthe selected memory cells to the read/write circuits 142 a and 142 b.For clarity, the address register 132, the row-address multiplexer 136,the row-address latch-and-decode circuits 138 a and 138 b, and thecolumn-address latch-and-decode circuit 144 can be collectively referredto as an address decoder.

47. A data input/output (I/O) circuit 146 includes a plurality of inputbuffers 148. During a write cycle, the buffers 148 receive and storedata from the DATA bus, and the read/write circuits 142 a and 142 bprovide the stored data to the memory banks 140 a and 140 b,respectively. The data I/O circuit 146 also includes a plurality ofoutput drivers 150. During a read cycle, the read/write circuits 142 aand 142 b provide data from the memory banks 140 a and 140 b,respectively, to the drivers 150, which in turn provide this data to theDATA bus.

48. A refresh counter 152 stores the address of the row of memory cellsto be refreshed either during a conventional auto-refresh mode orself-refresh mode. After the row is refreshed, a refresh controller 154updates the address in the refresh counter 152, typically by eitherincrementing or decrementing the contents of the refresh counter 152 byone. Although shown separately, the refresh controller 154 may be partof the control logic 134 in other embodiments of the memory circuit 130.

49. The memory circuit 130 may also include an optional charge pump 156,which steps up the power-supply voltage V_(DD) to a voltage V_(DDP). Inone embodiment, the pump 156 generates V_(DDP) approximately 1-1.5 Vhigher than V_(DD). The memory circuit 130 may also use V_(DDP) toconventionally overdrive selected internal transistors.

50. Although an embodiment of the row-address latch-and-decode circuits138 a and 138 b is described as including the matrix and redundantcontrol circuits 42 and 32 (FIGS. 5 and 6, respectively), any portion ofthe memory circuit 130 can include the fuse bank 60 (FIGS. 4A and 4B).

51.FIG. 10 is a block diagram of an electronic system 160, such as acomputer system, that includes the memory circuit 130 of FIG. 9. Thesystem 160 includes computer circuitry 162 for performing computerfunctions, such as executing software to perform desired calculationsand tasks. The circuitry 162 typically includes a processor 164 and thememory circuit 130, which is coupled to the processor 164. One or moreinput devices 166, such as a keyboard or a mouse, are coupled to thecomputer circuitry 162 and allow an operator (not shown) to manuallyinput data thereto. One or more output devices 168 are coupled to thecomputer circuitry 162 to provide to the operator data generated by thecomputer circuitry 162. Examples of such output devices 168 include aprinter and a video display unit. One or more data-storage devices 170are coupled to the computer circuitry 162 to store data on or retrievedata from external storage media (not shown). Examples of the storagedevices 170 and the corresponding storage media include drives thataccept hard and floppy disks, tape cassettes, and compact disk read-onlymemories (CD-ROMs). Typically, the computer circuitry 162 includesaddress data and command buses and a clock line that are respectivelycoupled to the ADDRESS, DATA, and COMMAND buses, and the CLK line of thememory circuit 130.

52. From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention.

What is claimed is:
 1. An integrated circuit, comprising: a firstconductive layer; an insulator layer disposed on the first conductivelayer; a second conductive layer disposed on the insulator layer; afirst fuse disposed in the first conductive layer and operable togenerate a first signal; and a second fuse disposed in the secondconductive layer in alignment with the first fuse and operable togenerate a second signal.
 2. The integrated circuit of claim 1 , furthercomprising: a substrate; and wherein the first and second conductivelayers and the insulator layer are disposed on the substrate.
 3. Theintegrated circuit of claim 1 wherein the first and second fusescomprise respective laser-openable fuses.
 4. The integrated circuit ofclaim 1 wherein: the first fuse is configured to open in response toexposure to an energy beam of a first frequency; and the second fuse isconfigured to open in response to exposure to an energy beam of a secondfrequency.
 5. The integrated circuit of claim 1 wherein: the first fuseis configured to open in response to exposure to a laser beam tuned to afirst frequency; and the second fuse is configured to open in responseto exposure to a laser beam tuned to a second frequency.
 6. Anintegrated circuit, comprising: a first conductive layer; an insulatorlayer disposed on the first conductive layer; a second conductive layerdisposed on the insulator layer; a first circuit having a first fusedisposed in the first conductive layer; and a second circuit having asecond fuse disposed in the second conductive layer in alignment withthe first fuse.
 7. The integrated circuit of claim 6 wherein: the firstcircuit comprises a matrix control circuit; and the second circuitcomprises a redundant control circuit.
 8. An integrated circuit,comprising: a first conductive layer; an insulator layer disposed on thefirst conductive layer; a second conductive layer disposed on theinsulator layer; first and second circuit nodes; a first fuse disposedin the first conductive layer and having a first terminal coupled to thefirst circuit node and having a second terminal uncoupled from thesecond circuit node; and a second fuse disposed in the second conductivelayer in alignment with the first fuse element and having a firstterminal coupled to the second circuit node and having a second terminaluncoupled from the first circuit node.
 9. The integrated circuit ofclaim 8 wherein the first and second circuit nodes are each disposed inone of the first and second conductive layers.
 10. The integratedcircuit of claim 8 , further comprising: at least one conductive layerin addition to the first and second conductive layers; and wherein thefirst and second circuit nodes are each disposed in the at least oneadditional conductive layer.
 11. The integrated circuit of claim 8 ,further comprising: a substrate; and wherein the first and secondconductive layers and the insulator layer are disposed on the substrate.12. The integrated circuit of claim 8 , further comprising: a thirdcircuit node; and wherein the second terminals of the first and secondfuses are coupled to the third circuit node.
 13. A fuse circuit,comprising: a first severable conductor configured to conduct a firstsignal; a second severable conductor aligned with the first conductorand configured to conduct a second signal; and an insulator disposedbetween the first and second conductors.
 14. The fuse circuit of claim13 wherein the second conductor is substantially vertically aligned withthe first conductor.
 15. A fuse bank, comprising: discrete fuses eachhaving two respective terminals, the fuses arranged in stacked pairs;and a fuse in each stacked pair having a terminal that is indirectlycoupled to a terminal of the other fuse in the same stacked pair.
 16. Afuse bank, comprising: discrete fuses each having two respectiveterminals, the fuses arranged in stacked pairs; and a fuse in eachstacked pair having a terminal that is electrically isolated from aterminal of the other fuse in the same stacked pair.
 17. A fuse array,comprising: a first fuse configured to conduct a first signal; and asecond fuse aligned with and electrically insulated from the first fuse,the second fuse configured to conduct a second signal.
 18. The fusearray of claim 17 , further comprising: a first conductive layer inwhich the first fuse is disposed; a second conductive layer in which thesecond fuse is disposed; and an insulator layer disposed between thefirst and second conductive layers.
 19. A fuse circuit, comprising: afirst fuse; a second fuse stacked on the first fuse and not electricallyparallel to the first fuse; and an insulator disposed between the firstand second fuses.
 20. The fuse circuit of claim 19 , further comprising:a first conductive layer in which the first fuse is disposed; a secondconductive layer in which the second fuse is disposed; and an insulatorlayer in which the insulator is disposed, the insulator layer disposedbetween the first and second conductive layers.
 21. An integratedcircuit, comprising: a first conductive layer; an insulator layerdisposed on the first conductive layer; a second conductive layerdisposed on the insulator layer; an address decoder operable to receivean address; an array of memory cells operable to store data, the arraycoupled to the address decoder; a read/write circuit coupled to thememory array and operable to read data from and write data to one ormore of the memory cells; a control circuit coupled to and operable tocontrol the address decoder and the read/write circuit; a first fusedisposed in the first conductive layer and coupled to and operable togenerate a first signal for the address decoder, array, read/writecircuit, or control circuit; and a second fuse disposed in the secondconductive layer in alignment with the first fuse and coupled to andoperable to generate a second signal for the address decoder, array,read/write circuit, or control circuit.
 22. An integrated circuit,comprising: a first conductive layer; an insulator layer disposed on thefirst conductive layer; a second conductive layer disposed on theinsulator layer; a memory array including a matrix memory cell having amatrix address and including a redundant memory cell; a matrix addressgenerator; a matrix circuit coupled to the memory array and to theaddress generator and including a matrix fuse disposed in one of thefirst and second conductive layers, the matrix fuse configured in afirst state in response to the matrix memory cell being functional andconfigured in a second state in response to the matrix memory cell beingdefective, the matrix circuit operable to fire the matrix memory cell inresponse to the matrix fuse having the first state; and a redundantcircuit coupled to the memory array and to the address generator andincluding a redundant fuse disposed in the other of the first and secondconductive layers in alignment with the matrix fuse, the redundant fuseconfigured in a third state in response to the matrix memory cell beingfunctional and configured in a fourth state in response to the matrixmemory cell being defective, the redundant circuit operable to fire theredundant memory cell in response to the redundant fuse having thefourth state.
 23. The integrated circuit of claim 22 wherein: the thirdstate equals the first state; and the fourth state equals the secondstate.
 24. The integrated circuit of claim 22 wherein: the fourth stateequals the first state; and the third state equals the second state. 25.An integrated circuit, comprising: a first conductive layer; aninsulator layer disposed on the first conductive layer; a secondconductive layer disposed on the insulator layer; a memory arrayincluding a matrix memory cell having a matrix address and including aredundant memory cell; a matrix address circuit for generating thematrix address; a redundant circuit coupled to the memory array and tothe matrix address circuit and including a redundant fuse disposed inone of the first and second conductive layers, the redundant fuseprogrammable in a first state to disable the redundant memory cell andprogrammable in a second state to map the redundant memory cell to thematrix address, the redundant circuit configured to fire the redundantmemory cell in response to the matrix address circuit generating thematrix address and the redundant fuse having the second state; and amatrix circuit coupled to the memory array and to the matrix addresscircuit and including a matrix fuse disposed in the other of first andsecond conductive layers in alignment with the redundant fuse, thematrix fuse programmable in a third state to enable the matrix memorycell and programmable in a fourth state to disable the matrix memorycell, the matrix circuit configured to fire the matrix memory cell inresponse to the matrix address circuit generating the matrix address andthe matrix fuse having the third state.
 26. The integrated circuit ofclaim 25 wherein: the matrix and redundant fuses comprise respectivelaser-openable fuses; the third state equals the first state; and thefourth state equals the second state.
 27. The integrated circuit ofclaim 25 wherein: the matrix fuse is configured to open in response toexposure to a laser beam having a first frequency; the redundant fuse isconfigured to open in response to exposure to a laser beam having asecond frequency; the fourth state equals the first state; and the thirdstate equals the second state.
 28. An integrated circuit, comprising: afirst conductive layer; an insulator layer disposed on the firstconductive layer; a second conductive layer disposed on the insulatorlayer; a memory array including a matrix memory cell, a matrix fireterminal coupled to the matrix memory cell, a redundant memory cell, anda redundant fire terminal coupled to the redundant memory cell; a matrixaddress circuit having an address output terminal; a redundant circuithaving an address input terminal coupled to the address output terminalof the matrix address circuit and having a firing terminal coupled tothe redundant fire terminal of the memory array, the redundant circuitincluding a redundant fuse disposed in one of the first and secondconductive layers, the redundant fuse programmable in a first state todisable the redundant memory cell and programmable in a second state tomap the redundant memory cell to the matrix address; and a matrixcircuit having an address input terminal coupled to the address outputterminal of the matrix address circuit and having a firing terminalcoupled to the matrix fire terminal of the memory array, the matrixcircuit including a matrix fuse disposed in the other of first andsecond conductive layers in alignment with the redundant fuse, thematrix fuse programmable in a third state to enable the matrix memorycell and programmable in a fourth state to disable the matrix memorycell.
 29. The integrated circuit of claim 28 wherein: the first andthird states comprise an electrically closed state; and the second andfourth states comprise an electrically opened state.
 30. An integratedcircuit, comprising: a first conductive layer; an insulator layerdisposed on the first conductive layer; a second conductive layerdisposed on the insulator layer; a memory array including a matrixmemory cell having a matrix address and including a redundant memorycell; a matrix address generator; a matrix-cell decoder coupled to thememory array and to the address generator and configured to activate thematrix memory cell in response to the address generator generating thematrix address and the matrix-cell decoder being enabled; a matrixcontrol circuit coupled to the matrix-cell decoder, the matrix controlcircuit including a matrix fuse disposed in one of the first and secondconductive layers and configured in a first state in response to thematrix memory cell being functional and configured in a second state inresponse to the matrix memory cell being defective, the matrix controlcircuit configured to disable the matrix-cell decoder from activatingthe matrix memory cell in response to the matrix fuse having the secondstate; a redundant-cell decoder coupled to the memory array and to theaddress generator and configured to activate the redundant memory cellin response to the address generator generating the matrix address andthe redundant-cell decoder being enabled; and a redundant controlcircuit coupled to the redundant-cell decoder, the redundant controlcircuit including a redundant fuse disposed in the other of the firstand second conductive layers in alignment with the matrix fuse, theredundant fuse configured in a third first state in response to thematrix memory cell being functional and configured in a fourth state inresponse to the matrix memory cell being defective, the redundantcontrol circuit configured to enable the redundant-cell decoder toactivate the redundant memory cell in response to the redundant fusehaving the fourth state.
 31. An integrated circuit, comprising: a firstconductive layer; an insulator layer disposed on the first conductivelayer; a second conductive layer disposed on the insulator layer; amemory array including a matrix memory cell having a matrix address andincluding a redundant memory cell; a matrix address generator; aredundant-cell decoder coupled to the memory array and to the matrixaddress generator and configured to map the redundant memory cell to thematrix address by firing the redundant memory cell in response to thematrix address generator generating the matrix address and theredundant-cell decoder being enabled; a redundant control circuitcoupled to the redundant-cell decoder, the redundant control circuitincluding a redundant fuse disposed in one of the first and secondconductive layers, the redundant fuse programmable in a first state tocause the redundant control circuit to enable the redundant-cell decoderto map the redundant memory cell to the matrix address and programmablein a second state to cause the redundant enable circuit to disable theredundant-cell decoder from mapping the redundant memory cell to thematrix address; a matrix-cell decoder coupled to the memory array and tothe matrix address generator and configured to fire the matrix memorycell in response to the matrix address generator generating the matrixaddress and the matrix-cell decoder being enabled; and a matrix controlcircuit coupled to the matrix-cell decoder, the matrix control circuitincluding a matrix fuse disposed in the other of first and secondconductive layers in alignment with the redundant fuse, the matrix fuseprogrammable in a third state to cause the matrix control circuit toenable the matrix-cell decoder to fire the matrix memory cell andprogrammable in a fourth state to cause the matrix control circuit todisable the matrix-cell decoder from firing the matrix memory cell. 32.An integrated circuit, comprising: a first conductive layer; aninsulator layer disposed on the first conductive layer; a secondconductive layer disposed on the insulator layer; a memory arrayincluding a matrix memory cell having a matrix address, a matrix fireterminal coupled to the matrix memory cell, a redundant memory cell, anda redundant fire terminal coupled to the redundant memory cell; anmatrix address circuit having an address output terminal; a matrix-celldecoder having an address input terminal coupled to the address outputterminal of the address circuit, a control terminal, and a firingterminal coupled to the matrix fire terminal of the memory array; amatrix control circuit having a control output terminal coupled to thecontrol terminal of the matrix-cell decoder, the matrix control circuitincluding a matrix fuse disposed in one of the first and secondconductive layers, coupled to the control output terminal, andconfigured in a first state in response to the matrix memory cell beingfunctional and configured in a second state in response to the matrixmemory cell being defective; a redundant-cell decoder having an addressinput terminal coupled to the address output terminal of the addresscircuit, a control terminal, and a firing terminal coupled to theredundant fire terminal of the memory array; and a redundant controlcircuit having a control output terminal coupled to the control terminalof the redundant-cell decoder, the redundant control circuit including aredundant fuse disposed in the other of the first and second conductivelayers, coupled to the control output terminal, and configured in athird first state in response to the matrix memory cell being functionaland configured in a fourth second state in response to the matrix memorycell being defective.
 33. An integrated circuit, comprising: a firstconductive layer; an insulator layer disposed on the first conductivelayer; a second conductive layer disposed on the insulator layer; amemory array including a matrix memory cell having a matrix address andincluding a redundant memory cell having a redundant address; a matrixaddress generator; a redundant address generator coupled to the matrixaddress generator and programmable to generate the redundant address inresponse to the matrix address generator generating the matrix address;a redundant-cell decoder coupled to the memory array and to theredundant address generator and configured to map the redundant memorycell to the matrix address by firing the redundant memory cell inresponse to the redundant address generator generating the redundantaddress and the redundant-cell decoder being enabled; a redundantcontrol circuit coupled to the redundant-cell decoder, the redundantcontrol circuit including a redundant fuse disposed in one of the firstand second conductive layers, the redundant fuse programmable in a firststate to cause the redundant control circuit to disable theredundant-cell decoder from mapping the redundant memory cell to thematrix address and programmable in a second state to cause the redundantenable circuit to enable the redundant-cell decoder to map the redundantmemory cell to the matrix address; a matrix-cell decoder coupled to thememory array and to the matrix address generator and configured to firethe matrix memory cell in response to the matrix address circuitgenerating the matrix address and the matrix-cell decoder being enabled;and a matrix control circuit coupled to the matrix-cell decoder, thematrix control circuit including a matrix fuse disposed in the other offirst and second conductive layers in alignment with the redundant fuse,the matrix fuse programmable in a third state to cause the matrixcontrol circuit to enable the matrix-cell decoder to fire the matrixmemory cell and programmable in a fourth state to cause the matrixcontrol circuit to disable the matrix-cell decoder from firing thematrix memory cell.
 34. An integrated circuit, comprising: a firstconductive layer; an insulator layer disposed on the first conductivelayer; a second conductive layer disposed on the insulator layer; amemory array including a matrix memory cell, a matrix fire terminalcoupled to the matrix memory cell, a redundant memory cell, and aredundant fire terminal coupled to the redundant memory cell; a matrixaddress circuit having an address output terminal; a redundant addresscircuit having an address input terminal coupled to the address outputterminal of the matrix address circuit and having a redundant addressoutput terminal; a redundant-cell decoder having an address inputterminal coupled to the redundant address output terminal of theredundant address circuit, a firing terminal coupled to the redundantfire terminal of the memory array, and a control terminal; a redundantcontrol circuit having a control output terminal coupled to the controlterminal of the redundant-cell decoder, the redundant control circuitincluding a redundant fuse disposed in one of the first and secondconductive layers, the redundant fuse having a first state that disablesthe redundant-cell decoder or having a second state that enables theredundant-cell decoder; a matrix-cell decoder having an address inputterminal coupled to the address output terminal of the matrix addresscircuit, a firing terminal coupled to the matrix fire terminal of thememory array, and a control terminal; and a matrix control circuithaving a control output terminal coupled to the control terminal of thematrix-cell decoder, the matrix control circuit including a matrix fusedisposed in the other of first and second conductive layers in alignmentwith the redundant fuse, the matrix fuse having a third state to enablethe matrix-cell decoder or having a fourth state to disable thematrix-cell decoder.
 35. An electronic system, comprising: a data inputdevice; a data output device; and a computer circuit coupled to the datainput and output devices and including a processor and a memory circuitcoupled to the processor, the memory circuit including: a firstconductive layer; an insulator layer disposed on the first conductivelayer; a second conductive layer disposed on the insulator layer; anaddress decoder operable to receive an address; an array of memory cellsoperable to store data, the array coupled to the address decoder; aread/write circuit coupled to the memory array and operable to read datafrom and write data to one or more of the memory cells; a controlcircuit coupled to and operable to control the address decoder and theread/write circuit; a first fuse disposed in the first conductive layerand coupled to and operable to generate a first signal for the addressdecoder, array, read/write circuit, or control circuit; and a secondfuse disposed in the second conductive layer in alignment with the firstfuse and coupled to and operable to generate a second signal for theaddress decoder, array, read/write circuit, or control circuit.
 36. Amethod, comprising the steps of: directing an energy beam at a firstfuse that shields a second fuse from the beam; opening the first fusewith the energy beam; and opening the second fuse with the beam afteropening the first fuse.
 37. The method of claim 36 wherein the energybeam comprises a laser beam.
 38. The method of claim 36 wherein: thefirst fuse is disposed in a first conductive layer of an integratedcircuit; and the second fuse is disposed in a second conductive layer ofthe integrated circuit.
 39. The method of claim 36 wherein: the step ofopening the first fuse comprises disabling a matrix cell; and the stepof opening the second fuse comprises enabling a redundant cell.
 40. Themethod of clam 36 wherein: the step of opening the first fuse comprisesenabling a redundant cell; and the step of opening the second fusecomprises disabling a matrix cell.
 41. A method, comprising the stepsof: directing a first energy beam at a first fuse that shields a secondfuse from the beam; opening the first fuse with the energy beam; andafter opening the first fuse, exposing the second fuse to the beamwithout opening the second fuse.
 42. The method of claim 41 , furthercomprising the steps of: directing a second energy beam at the secondfuse after exposing the second fuse to the first energy beam; andopening the second fuse with the second energy beam.
 43. The method ofclaim 41 , further comprising the steps of: generating the first energybeam having a first frequency; directing a second energy beam having asecond frequency at the second fuse after exposing the second fuse tothe first energy beam; and opening the second fuse with the secondenergy beam.
 44. The method of claim 41 , further comprising the step ofgenerating the first energy beam from a laser beam.
 45. A method,comprising the steps of: configuring a first fuse to conduct a firstsignal; and configuring a second fuse to conduct a second signal, thesecond fuse being aligned with the first fuse.
 46. The method of claim45 , further comprising the step of opening the first fuse withoutopening the second fuse.
 47. The method of claim 45 , further comprisingthe steps of: opening the first fuse; and opening the second fuse via abreak in the first fuse.
 48. A method, comprising the steps of: forminga first fuse; forming a second fuse that is aligned with and notelectrically in parallel with the first fuse; and forming an insulatorbetween the first and second fuses.
 49. The method of claim 48 wherein:the step of forming a first fuse comprises: forming a first conductivelayer; and forming the first fuse in the first conductive layer; thestep of forming the second fuse comprises: forming a second conductivelayer; and forming the second fuse in the second conductive layer; andthe step of forming the insulator comprises forming an insulator layerbetween the first and second conductive layers.
 50. A method, comprisingthe steps of: forming a first fuse having a first terminal coupled to afirst node; and stacking a second fuse onto the first fuse, the secondfuse having a first terminal coupled to a second node.
 51. The method ofclaim 50 wherein: the step of forming the first fuse comprises: forminga first conductive layer; and forming the first fuse in the firstconductive layer; and the step of stacking the second fuse comprises:forming a second conductive layer that is insulated from the firstconductive layer; and forming the second fuse in the second conductivelayer.
 52. The method of claim 50 wherein the step of forming the firstfuse comprises forming the first fuse having a second terminal coupledto the second node.
 53. The method of claim 50 wherein: the step offorming the first fuse comprises forming the first fuse having a secondterminal coupled to a third node; and the step of forming the secondfuse comprises forming the second fuse having a second terminal coupledto a fourth node.